Making a reversible circuit fault-tolerant is much more difficult thanclassical circuit and there have been only a few works in the area ofparity-preserving reversible logic design. Moreover, all of these designs aread hoc, based on some pre-defined parity preserving reversible gates asbuilding blocks. In this paper, we for the first time propose a novel andsystematic approach towards parity preserving reversible circuits design. Weprovide some related theoretical results and give two algorithms, one fromreversible specification to parity preserving reversible specification andanother from irreversible specification to parity preserving reversiblespecification. We also evaluate the effectiveness of our approach by extensiveexperimental results.
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